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Technology Marketing and Development Consulting Ltd
Auckland, New Zealand

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Differential GPS (DGPS) Receiver and DSP Radio Modem

TMD have developed a Digital Signal Processing board based on the low-cost Texas Instruments (TI) range of single chip DSP processors. 

Code has been developed for this board to implement a full two channel scanning Differential GPS (DGPS) beacon receiver for decoding RTCM104 GPS correction data transmitted by US Coast Guard beacons. The board is designed around the low-cost, flash based TMS320LF2406 processor but the code will also run on other family members (such as TMS320LF2404, TMS320LF243) depending on required features (e.g., number of channels, data speed etc).

Note that code to implement the Differential GPS (DGPS) beacon receiver is available for OEM applications allowing DGPS to be added to existing GPS designs for less than US$9.00 (excluding antenna).

For more information on DGPS receivers or DSP based modems, please Contact TMD.

DSP-DGPS

PCB shown with SMD TMS320LF2406 processor. Also shown with PIC controller used to interface to host GPS system. To keep costs down in OEM applications, the GPS processor can communicate direct with the DSP through a simple communications port. In this mode, the DSP acts as a peripheral to the GPS engine.

Dimensions: 76(w) x51(d) (3" x 2")

Differential GPS (DGPS) unit shown prior to assembly in case. GPS patch antenna visible on top and torroidal beacon receiver antenna in centre. 

Differential GPS (DGPS) unit shown fully assembled. This product is supplied by Talon Technology and can be viewed at Navman Marine Products, DGPS Smart Antenna.

 

Technical Details

The DSP code runs on a single chip TI processor and integrates all of the following receiver and system functions to process and extract 200bits/sec DGPS beacon correction data (transmitted in RTCM 104 format):

Receiver IF frequency interface at 455KHz.

DSP onboard 10-bit A/D.

Downconversion to zero frequency IF with high resolution NCO.

Channel frequency selection within IF band  500Hz steps.

Automatic Fine Frequency adjustment (+/- 20Hz).

Sample rate decimation to KHz baseband rate.

Variable bandwidth FIR filter to match selected data rate (50–100–200 bits/sec).

Precision FM demodulator with high order AM rejection.

Overall signal scaling within DSP.

External AGC control if required using PWM analog outputs.

Bit timing recovery loop.

Frame synchronizing  and data packet CRC checking.

Serial data formatting and output.

Serial data input and command interpretation.

Alternative parallel control input.

Driver for external EEPROM for parameters.

Boot loader for on- board flash programming up to 32Kbytes.

JTAG port for development, testing and alternative flash programming.

Future enhancements and additional capabilities

Modulator for incoming data stream.

Forward error and interleaving encoding.

Faster bit rate up to 1200 bits/sec.

Error correction in receive path.

Analog I and Q outputs from on board PWM outputs for upconverter.

Control outputs for driving external frequency synthesizer and transceiver functions.

CAN bus interface.

  Advantages

Low power 3.3V operation.

Low EMI single chip solution.

Low cost processor.

 

 

TMD Consultants, 1st Floor, 15 Rawene Rd, P.O Box 34-338, Birkenhead, Auckland, New Zealand. Tel: +64 9 419-1925, Fax: +64 9 419-7984.

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Last modified: June 10, 2003